As a digital device progresses to have high functions, since a capacity of contents handled by a user is increased, a high speed and large capacity communication is demanded. Further, as a CMOS process is developed to be very minute, a prospect is established that a transmission of Giga bit class using a milliwave may be realized. In this case, a high frequency IC which is compliant with a milliwave wireless communication is desirably inexpensive and has a low consumed power.
A down converting system using the high frequency IC has a Superheterodyne system and a direct conversion system. In the Superheterodyne system, a high frequency signal is temporarily down converted into an intermediate frequency, and after a down converting process, the signal is converted into a base band signal. On the other hand, in the down conversion system, the high frequency signal is not down converted into such intermediate frequency, but directly converted into a base band signal. Accordingly, the high frequency IC of the direct conversion system can have a circuit scale more reduced and is more suitable for a low cost and the low consumed power than that of the Superheterodyne system.
FIG. 11 is a diagram showing a structure of an orthogonal modulation receiving circuit including QPSK using the direct conversion system. In the receiving circuit, since a frequency of input signals to mixers 12 and 13 is equal to a frequency of a local oscillation signal (RF Local), a local leak arises that the local oscillation signal is transferred to pre-stages of the mixers 12 and 13.
As a result, a self mixing is generated in the mixers 12 and 13 to generate DC offsets. Signals including the DC offsets are amplified in variable gain amplifiers (VGA) 14 and 15 to vary DC offset components due to the self mixing. Accordingly, proper signals are hardly amplified in the VGAs 14 and 15, thereby to lead to a degradation of a communication quality.
Accordingly, the receiving circuit of the direct conversion system needs to use DC offset correcting circuits which correct the DC offsets in the VGAs 14 and 15 at the same time.
Patent Literature 1 discloses a technique that provides offset correcting circuits (OFC) respectively for variable gain amplifiers (PGA) to correct DC offsets in order from a first stage PGA to post-stage PGAs.
FIG. 12 is a block diagram showing a receiving circuit of a direct conversion system disclosed in Patent Literature 1. In the circuit shown in FIG. 12, in order to perform a correction of the DC offset under a non-input state, a power supply of an LNA is turned off. Then, in order to correct the DC offset to a PGA1, the DC offset is detected in an ADC1 in the offset correcting circuit 1 (OFC1).
A control circuit 240 determines a DC offset correction amount and applies a control voltage to the correcting circuit in the PGA1 through a DAC1 in the offset correcting circuit (the OFC1) to correct the DC offset.